This invention relates generally to MOS (metal oxide semiconductor) memories, and is particularly directed to a high speed, low power RAM (random access memory) having a redundancy scheme for replacing defective memory cells with spare memory cells.
MOS memories generally include a memory array in the form of rows and columns of memory cells for storing digital data. In a typical memory, there may be more than sixteen thousand individual memory cells, each of which must function properly. A single inoperative memory cell destroys the usefulness of the memory and, therefore, lowers the yield of the wafer on which many memories are simultaneously manufactured.
To increase the yield of each wafer, it has been proposed to include spare memory cells in each chip. Thus, if a memory cell is found to be defective during testing by the manufacturer, a spare memory cell is selected to replace the defective memory cell.
Some prior schemes for selecting spare memory cells have included the use of fuses which are embodied in each chip in such a way that blowing a fuse with a laser beam causes a defective cell to be replaced by a spare cell.
In some other schemes for selecting a spare memory cell, a fuse is blown electrically in response to an externally derived test signal during probe test and a simultaneous low level signal at an address input. The latter signal is typically coupled directly to the fuse via a transistor such that the current required to blow the fuse passes through the transistor to the address input. Hence, the address input must be able to draw current in order to blow the fuse and this places undesirable current handling restraints on the test equipment which applies test signals to the address inputs. In addition, the above-mentioned transistor suffers from a lack of input protection.
Electrical fuse-blowing schemes of the type described above typically require external clock pulses to gate the fuse information to additional sensors which, in turn, generate address information identifying the defective cells. The time required to generate the address information relating to the defective memory cells adds to the time required to complete a read or write operation.
Another drawback of prior redundancy schemes, both of the laser fuse-blowing type and the electrical fuse-blowing type, is that they tend to be complex. A more desirable redundancy scheme would not only blow the fuses electrically, but would use less complex on-chip circuitry which imposes no access time penalty and which dissipates very little chip power.